1. Field of the Invention
The present invention generally relates to divide-by-N circuits for dividing the frequency of a master clock signal in order to obtain a clock signal having a different frequency from that of the master clock signal (also known as frequency dividers). The present invention more particularly relates to a frequency dividing circuit that divides the frequency of a master clock signal by a non-integer.
2. Background Art
Divide-by-N counters (or circuits) are well-known circuits that are used to divide the frequency of a clock signal (e.g., a system clock) by a specific number of counts. That is, for N clock pulses input into the circuit, only one output pulse is generated.
These frequency dividers are used for many different applications. In particular, frequency dividers are used to reduce the overall number of oscillators required on a given semiconductor chip, thereby making available additional room on the chip to place as much other circuitry as possible. Often, a single oscillator circuit is provided that generates a master clock signal. One or more frequency dividers are then used to generate clock signals having different frequencies. Typically, one or more divide-by-2 circuits are used to divide the master oscillator clock frequency by a factor of 2, 4, 8, etc.
It would be desirable to provide a frequency divider that can divide a master clock signal by a non-integer factor. In addition, it would be desirable to have such a frequency divider that can be used for very high speed applications (e.g.  greater than 1 Ghz), and that provides a clock signal having very low jitter.
According to an aspect of the invention, a frequency dividing circuit is provided that divides a master clock frequency by a noninteger factor to provide an output clock signal whose frequency is equal to the frequency of the master clock signal divided by that non-integer factor. In one embodiment, the circuit is operative to divide the master clock frequency by 2.5, but circuits that are operative to divide the master clock frequency by other non-integer factors can be designed.
In one embodiment, the circuit incorporates a conventional Johnson counter, and a plurality of stages, with the respective stages being clocked with a phase-shifted version of the master clock signal. Various OR logic operations are performed on the outputs from the different stages to achieve the divide-by-2.5 output clock signal.
Thus, in one illustrative embodiment, the invention is directed to a frequency divider that is operative to divide a master clock signal by a non-integer factor, including a plurality of flip flops, each of the flip flops being clocked with a first clock signal, and the output of each flip flop being introduced to the adjacent flip flop and to a NOR gate, with the output of the NOR gate being introduced to the first flip flop, the divider further including a plurality of stages, each being clocked by a phase-shifted version of the first clock signal, with the outputs of the stages being introduced to respective OR logic operations to arrive at the frequency divided clock signal.
In another embodiment, the invention is directed to a method of generating an output clock signal whose frequency is equal to a master clock signal frequency divided by a non-integer factor, the method including clocking the respective flip flops of a Johnson counter with the master clock signal, and providing outputs from respective ones of those flip flops to various stages, with the respective stages being clocked by phase-shifted versions of the master clock signal, and then combining the outputs from the respective stages to achieve the frequency-divided output clock signal.
In another embodiment, the invention is directed to a method of generating an output clock signal whose frequency is equal to a master clock signal frequency divided by a non-integer factor, the method including receiving a master clock signal, using the master clock signal to clock a sequential counter having multiple outputs, introducing the respective outputs from the counter to respective stages, where each stage is clocked by a phase-shifted version of the master clock signal, and combining the outputs from the respective stages to generate the frequency-divided output clock signal.